EDN

Cadence, Mentor team on SystemVerilog verification

LONDON — Two EDA companies, Cadence Design Systems Inc. and Mentor Graphics Corp., have joined forces to promote a common approach to the verification of design files based on the SystemVerilog ...
Electronic Design

Cadence, Mentor Graphics agree on SystemVerilog verification

Cadence Design Systems (www.cadence.com) and Mentor Graphics (www.mentor.com) have agreed to standardize on an open source methodology for verifying SystemVerilog design files. Cadence Design Systems ...
Design-Reuse

OKI Turns to Cadence and the Open Verification Methodology (OVM) to Speed Product Development

OVM Enables OKI to Improve Verification IP Integration and Compress Testbench Development by 30% SAN JOSE, Calif. -- 29 Jul 2008-- Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global ...
New Electronics

Cadence and Imperas support NSITEXE in development of automotive RISC V Vector processor IP

Imperas Software and Cadence Design Systems have collaborated to enable NSITEXE, part of the DENSO Corporation, to develop a RISC-V-based processor IP for functional safety and next-generation ...