The huge undertaking of verifying a system-on-chip (SoC) design has challenged engineers for more than 20 years –– the amount of time spent on it hasn’t varied much from between 50-70% of the entire ...

The most effective functional verification environments employ multiple analysis technologies, where the strengths of each are combined to reinforce each other to help ensure that the device under ...

Assertions have been key contributors in increasing confidence in the accuracy of the design & quality of verification since coding effective coverage is fundamental in ensuring the completeness of ...

For years the process of ASIC and FPGA design and verification debug consisted primarily of comprehending the structure and source code of the design with waveforms showing activity over time, based ...

This paper presents functional coverage analysis automation and an approach to scale down overall simulation time. It is well known that functional verification of configurable IP cores is a real ...

Lowering the power consumption and leakage in SoCs and other electrical designs has become a paramount concern in recent years. The reasons for this are many and well understood. The structures and ...

You certainly can’t improve something unless you measure it. So, how do you know if the functionality of your design has been verified completely? One metric that helps answer this question is ...

PARTNER CONTENT Given the size and complexity of modern semiconductor designs, functional verification has become a dominant phase in the development cycle. Coverage lies at the very heart of this ...