EDN

PathPartner Technology Announces Industry’s First Hybrid Hardware-Software HEVC Decoder Optimized for Programmable SoC Devices

Hybrid HEVC Decoder uses ARM CPU and FPGA fabric optimally enabling flexible, highly integrated video systems at lower overall system cost PathPartner Technology, a leading provider of embedded ...
EDN

TELEVISION IP: Programmable core boosts processing On Demand

Paris – Intellectual-property licensing company On Demand Microelectronics GmbH is quietly making inroads into the digital TV market by leveraging the programmability of its synthesizable core. The ...
Hackaday

Emulating A 74LS48 BCD-to-7-Segment Decoder/Driver With An Altera MAX 7000 “S” Series Complex Programmable Logic Device

Over on the [Behind The Code with Gerry] YouTube channel our hacker [Gerry] shows us how to emulate a 74LS48 BCD-to-7-segment decoder/driver using an Altera CPLD Logic Chip From 1998. This is very ...
Semiconductor Engineering

An 8 Bit To 12 Bit Resolution Programmable 5 MSample/s Current Steering Digital-To-Analog Converter In A 22 nm FD-SOI CMOS Technology

We present a 5 MSample/s current steering digital-to-analog converter which has a programmable resolution between 8 bit, 10 bit and 12 bit. A selectable 2-D unary matrix architecture and a resolution ...