EDN

Mixed-mode verification of DDR, LCD, and memory sub-systems: Verilog-AMS vs. SPICE

Editor's note: This paper is the third in a series covering the pros and cons of using a Verilog-AMS view with respect to a SPICE view for verification of SOC IP having an analog component. The first ...
Design-Reuse

Digital Blocks DMA Controller Verilog IP Core Family Extends Leadership with enhancements to AXI4 Memory Map and Streaming Interfaces

GLEN ROCK, New Jersey, January 2, 2023 – Digital Blocks, a leading developer of silicon-proven semiconductor Intellectually Property (IP) soft cores for system-on-chip (SoC) ASIC, ASSP, & FPGA ...